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JEDEC JESD8-4ADDENDUM No. 4 to JESD8 - CENTER-TAP-TERMINATED (CTT) INTERFACE LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITSstandard by JEDEC Solid State Technology Association, 11/01/1993
JEDEC JESD 27 [ Withdrawn ]CERAMIC PACKAGE SPECIFICATION FOR MICROELECTRONIC PACKAGESstandard by JEDEC Solid State Technology Association, 08/01/1993
JEDEC JESD8-2ADDENDUM No. 2 to JESD8 - STANDARD FOR OPERATING VOLTAGES AND INTERFACE LEVELS FOR LOW VOLTAGE EMITTER-COUPLED LOGIC (ECL) INTEGRATED CIRCUITSstandard by JEDEC Solid State Technology Association, 03/01/1993
JEDEC JESD 12-1BADDENDUM No. 1 to JESD12 - TERMS AND DEFINITIONS FOR GATE ARRAYS AND CELL-BASED INTEGRATED CIRCUITSAmendment by JEDEC Solid State Technology Association, 08/01/1993
JEDEC JESD18-ASTANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGICstandard by JEDEC Solid State Technology Association, 01/01/1993
JEDEC JEP118GUIDELINES FOR GaAs MMIC AND FET LIFE TESTINGstandard by JEDEC Solid State Technology Association, 01/01/1993
JEDEC JESD 320-A (R2002)CONDITIONS FOR MEASUREMENT OF DIODE STATIC PARAMETERSstandard by JEDEC Solid State Technology Association, 12/01/1992
JEDEC JESD 37STANDARD LOGNORMAL ANALYSIS OF UNCENSORED DATA, AND OF SINGLY RIGHT -CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHODstandard by JEDEC Solid State Technology Association, 10/01/1992
JEDEC JESD 24-8 (R2002)ADDENDUM No. 8 to JESD24 - METHOD FOR REPETITIVE INDUCTIVE LOAD AVALANCHE SWITCHINGAmendment by JEDEC Solid State Technology Association, 08/01/1992
JEDEC JESD 24-9 (R2002)ADDENDUM No. 9 to JESD24 - SHORT CIRCUIT WITHSTAND TIME TEST METHODAmendment by JEDEC Solid State Technology Association, 08/01/1992
JEDEC JES 2TRANSISTOR, GALLIUM ARSENIDE POWER FET, GENERIC SPECIFICATIONstandard by JEDEC Solid State Technology Association, 07/01/1992
JEDEC JEP116CMOS SEMICUSTOM DESIGN GUIDELINESstandard by JEDEC Solid State Technology Association, 11/01/1991