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JEDEC JESD51-4THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)standard by JEDEC Solid State Technology Association, 02/01/1997
JEDEC JESD57TEST PROCEDURE FOR THE MANAGEMENT OF SINGLE-EVENT EFFECTS IN SEMICONDUCTOR DEVICES FROM HEAVY ION IRRADIATIONstandard by JEDEC Solid State Technology Association, 12/01/1996
JEDEC JEP128GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTINGstandard by JEDEC Solid State Technology Association, 11/01/1996
JEDEC JESD8-8ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITSstandard by JEDEC Solid State Technology Association, 08/01/1996
JEDEC JESD 24-11 (R2002)ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHODAmendment by JEDEC Solid State Technology Association, 08/01/1996
JEDEC JESD51-3LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGESstandard by JEDEC Solid State Technology Association, 08/01/1996
JEDEC JEP103A (R2003)SUGGESTED PRODUCT-DOCUMENTATION, CLASSIFICATIONS, AND DISCLAIMERSstandard by JEDEC Solid State Technology Association, 07/01/1996
JEDEC JESD 36STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICESstandard by JEDEC Solid State Technology Association, 06/01/1996
JEDEC EIA 318-BMEASUREMENT OF REVERSE RECOVERY TIME FOR SEMICONDUCTOR SIGNAL DIODESstandard by JEDEC Solid State Technology Association, 07/01/1996
JEDEC JESD32STANDARD FOR CHAIN DESCRIPTION FILEstandard by JEDEC Solid State Technology Association, 06/01/1996
JEDEC JEP126GUIDELINE FOR DEVELOPING AND DOCUMENTING PACKAGE ELECTRICAL MODELS DERIVED FROM COMPUTATIONAL ANALYSISstandard by JEDEC Solid State Technology Association, 05/01/1996
JEDEC JESD55STANDARD FOR DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE BiCMOS LOGIC DEVICESstandard by JEDEC Solid State Technology Association, 05/01/1996