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JEDEC JEP171
M00001671
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JEDEC JEP171 GDDR5 Measurement Procedures
standard by JEDEC Solid State Technology Association, 2014
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Full Description
This publication is to inform all industry participants of a unified procedure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5.This document provides the test methodology details on: CK and WCK Timings: tCK, tWCK, tCH/tCL, tWCKH/tWCKL, CK TJ/RJrms, CK and WCK JitterCK and WCK Input Operating Conditions: VIXCK, VIXWCK, VIDCK(ac), VIDWCK(ac), VIDCK(dc),VIDWCK(dc), CKslew, and WCKslewData Input Timings: tDIVW, tDIPWNote: The procedures described in this document are intended to provide information about the tests that will be used in JEDEC GDDR5 recommended measurement parameter. This testing is not a replacement for an exhaustive test validation plan.